Digital System Design(DSD) Syllabus

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This page contains Syllabus of Digital System Design of CSIT.

Title Digital System Design
Short Name DSD
Course code CSC417
Nature of course Theory + Lab
Semester seventh-semester
Full marks 60+20+20
Pass marks 24+8+8
Credit Hrs 3
Elective/Compulsary Elective

Course Description

Course Description:

This course contains the introductory part of combinational Logic along with the clear concepts of K-Maps and Quine- Mc Cluskey Method. It also introduces sequential networks with flip flops and FSM. Another concept includes FPGA and VHDL and also testing and verification.

Course Objective:

The course objective is to provide ample knowledge on digital design process and to enhance the knowledge of hardware design in real scenarios.

Units and Unit Content

1. Unit 1
teaching hours: 5 hrs

Introduction of logic design, Digital System and Integration, Electronic Design Automation, IC Manufacturing, Logic Families, IC Design Techniques, IC characteristics: fan-out, power dissipation, propagation delay, and noise margin of TTL and CMOS integrated circuit logic devices

2. Unit 2
teaching hours: 4 hrs

Review of Boolean Algebra and Combinational Logic, Canonical Form, Shannon's Expansion, Minterms, Maxterms, Prime Implication

3. unit 3
teaching hours: 5 hrs

Combinational Network Design: K – Map, Synthesis and Minimization with K – Maps (AND – OR, OR-AND, NAND-NAND, NOR-NOR), Standard Combinational Networks

4. Unit 4
teaching hours: 7 hrs

Quine- Mc Cluskey Method, Minimization of Boolean expression with Quine-Mc Cluskey method, PROMs and EPROMs, Programmable Array Logic (PAL), Programmed Logic Array (PLA), Gate Arrays, Programmable Gate Array, Full Custom Design

5. Unit 5
teaching hours: 8 hrs

Sequential Networks: Transition from combinational to sequential network, Direct command flip flop, Initialization of sequential network, Level Enabled Flip-Flops, Synchronization of sequential networks, Edge-triggered Flip Flops, Synchronous and Asynchronous Signals

6. Unit 6
teaching hours: 6 hrs

Sequential Networks as Finite State Machines: Standard Models, Realization with ASM Diagrams, Synthesis of Synchronous FSM, Time Behavior of Synchronous FSM, Design of input forming, Logic and Output Forming Logic of state machine.

7. Unit 7
teaching hours: 4 hrs

Field Programmable Gate Arrays (FPGA), VHDL and its use in programmable logic devices (PLDs) like FPGA

8. Unit 8
teaching hours: 6 hrs

Testing and Verification, Testing Logic Circuits, Combinational gate testing, Combinational network testing, Sequential Testing, Test vector generation, fault, fault model and fault detection, SA0, SA1, Design for Testability

Lab and Practical works

Laboratory Works:

Laboratory Exercise should cover the implementation of combinational and sequential circuits, FSM, FPGA and VHDL. Testing and verification of circuits.

Project Work:

Design a sample of tool kit by using the design concepts of the course.