# Digital Logic(DL) Syllabus

 Title Digital Logic Short Name DL Course code CACS105 Nature of course Theory + Practical Semester first-semester Full marks 60 + 20 + 20 Pass marks 24 + 8 + 8 Credit Hrs 3 Elective/Compulsary Compulsary

### Course Description

Course Description

This course presents an introduction to Digital logic techniques and its practical application in computer and digital system.

Course Objectives

The course has the following specific objectives:

• To perform conversion among different number systems

• To simplify logic functions

• To design combinational and sequential logic circuit

• To understand industrial application of logic system.

• To understand Digital IC analysis and its application

• Designing of programmable memory

### Units and Unit Content

1. Introduction
teaching hours: 2 hrs

1.1 Digital Signals and Wave Forms

1.2 Digital Logic and Operation

1.3 Digital Computer and Integrated Circuits(IC)

1.4 Clock Wave Form

2. Number Systems
teaching hours: 5 hrs

2.1 Binary, Octal, & Hexadecimal Number Syatems and Their Conversions

2.1.1 Representation of Signed Numbers-Floating Point Number

2.1.2 Binary Arithmetic

2.2 Representation of BCD- ASCII-Excess 3 -Gray Code - Error Detecting and Correcting Codes.

3. Combinational Logic Design
teaching hours: 16 hrs

3.1 Basic Logic Gates NOT, OR and AND

3.2  Universal Logic Gates NOR and NAND

3.3 EX-OR and EX-NOR Gates

3.4 Boolean Algebra:

3.3.1 Postulates & Theorems

3.3.2 Canonical Forms- Simplification of Logic Functions

3.5 Simplification of Logic Functions Using karnaugh Map.

3.5.1 Analysis of SOP and POS Expression

3.6 Implementation of Combinational Logic Functions

3.6.1 Encoders & Decoders

3.7 Implementation of Data Processing Circuits

3.7.1 Multiplexers and De-Multiplexers

3.7.2 Parallel Adder -Binary Adder- Parity Generator/Checker-Implementation of Logical     Functions Using Multiplexers.

3.8 Basic Concepts of Programmable Logic

3.8.1 PROM

3.8.2 EPROM

3.8.3 PAL

3.8.4 PLA

4. Counters & Registers
teaching hours: 16 hrs

4.1 RS, JK, JK Master- Slave, D & T Flip flops

4.1.1 Level Triggering and Edge Triggering

4.1.2 Excitation Tables

4.2 Asynchronous and Synchronous Counters

4.2.1 Ripple Counter: Circuit and State Diagram and Timing Waveforms

4.2.2 Ring Counter: Circuit and State Diagram and Timing Waveforms

4.2.3 Modulus 1 Counter: Circuit and State Diagram and Timming Waveforms

4.2.4 Modulus Counters (5, 7, 11) and Design Principle, Circuit and State Diagram

4.2.5 Synchronous Design of Above Counters, Circuit Diagrams and State Diagrams

4.3 Application of Counters

4.3.1 Digital Watch

4.3.2 Frequency Counter

4.4 Registers

4.4.1 Serial in Parallel out Register

4.4.2 Serial in Serial out Register

4.4.3 Parallel in Serial out Registor

4.4.4 Parallel in Parallel out Registor

4.4.5 Right Shift, Left Shift Registor

5. Sequential Logic Design
teaching hours: 6 hrs

5.1 Basic Models of Sequential Machines

•     Concept of State
•     State Diagram

5.2 State Reduction through Partitioning and Implementation of Synchronous Sequential Circuits

5.3 Use of Flip-Flops in Realizing the Models

5.4 Counter Design

### Lab and Practical works

Laboratory Works

1. Gates using Active and Passive Elements